Cadence and Arm launch ADAS chiplet development platform


Cadence Design Systems and Arm have announced they are collaborating to deliver a chiplet-based reference design and software development platform, initially for advanced driver assistance system (ADAS) applications, where it specifies a scalable chiplet architecture and interface interoperability to address challenges around enabling industry-wide collaboration on heterogeneous integration.

With much focus in the automotive industry enabling platforms for software-defined vehicles (SDVs), and with ADAS systems increasingly becoming more sophisticated, this is driving the need for more complex AI and software capabilities, as well as greater levels of interoperability and collaboration in the automotive electronics ecosystem.

Cadence auto image
(Image: Cadence)

Although chiplets are not new conceptually, they are now considered a way of modularizing the efforts of quickly putting together customized 3D-IC systems for a plethora of automotive applications.

However, the big issue is how to make chiplets from different IP providers work together seamlessly. The rapid pace of automotive development necessitates that 3D-IC system developers have a software development platform to, as Cadence says, “shift left” in the process flow while the IP and chiplets are still being designed.

Chiplets promise to cut down development cycles by enabling concurrent design and assembly of multiple chips using a common, standardized interface, as long as chiplets from different vendors and with different applications can seamlessly interoperate.

The Cadence and Arm solution is architected and built using the latest generation of Arm Automotive Enhanced technologies and Cadence IP. The complementary software stack development platform is provided as a digital twin of the hardware that is compliant with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative software standard, enabling software development to begin before hardware is available and allowing subsequent system integration validation. The combined solution speeds both hardware and software development, accelerating time-to-market.

The new Cadence and Arm solution architecture and reference design provide a standard for chiplet interface interoperability. The Cadence components of the solution include:

  • Helium Virtual and Hybrid Studio for the rapid creation of virtual and hybrid platforms and Helium Software Digital Twin to support deployment at scale for software developers
  • I/O IP solutions for industry-leading interface and memory protocols, including Universal Chiplet Interconnect Express (UCIe) for high-speed chiplet-to-chiplet communication
  • Comprehensive compute IP portfolio including advanced AI solution, the Neo neural processing unit (NPU) IP, the NeuroWeave software development kit (SDK) for machine learning (ML) solutions, and world-class DSP compute solutions

“The automotive industry is evolving rapidly and AI and software advancements are emphasizing a greater need to speed up development cycles,” said Dipti Vachani, senior vice president and general manager for the automotive line of business at Arm. “Together with critical ecosystem partners like Cadence, we’re enabling faster software and hardware development by bringing together a complete solution of design and verification technologies underpinned by the latest Automotive Enhanced technologies from Arm, allowing developers to start building for next-generation SDVs well before silicon is available in the market.”

For Cadence, senior vice president and general manager of the system verification group, Paul Cunningham, added, “Reducing the overall system design workload and shifting hardware and software development left are both crucial to meet shrinking time-to-market windows when developing today’s increasingly complex SDVs. Virtual platforms and chiplets are both key enablers for automotive 3D-IC SoC developers. Working closely with Arm, we are addressing key inefficiencies in both software and hardware development and verification processes, while catalyzing the multi-die chiplet ecosystem for automotive semiconductors.”

The virtual platform and component IP for the reference platform are available now for early adopters.

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